Conventional very large scale integrated circuit (VLSI) systems rely on System on a Chip (SoC) to achieve higher performance and receive more diversified architectures. As the chip function becomes more diversified and complex, and clock frequency and total number of transistors decrease gradually, total leakage power becomes more severe. Design of low power circuits, therefore, becomes very important to reduce power consumption of the chip becomes a big issue and research focus at present.
Because the SoC clock circuit and storage circuit are the main cause of power loss, design of a lower power storage element becomes a critical factor to reduce total power consumption of SoC.
Flip-Flop (FF) is an important and widely used storage element, especially on mobile devises such as notebook computers, personal digital assistants (PDAs) and cell phones. Hence, design of flip-flop plays a big role to meet such a requirement for providing a higher performance at a lower power. In SoC applications clock system (including clock distribution networks and storage elements) consumes power about 20% to 45% of total system. In the clock system the number of transistors and power consumption mostly are taken by the flip-flops. Thus reducing the power consumption of the flip-flop can greatly improve total power performance.
At present on research of the flip-flop, pulse-triggered flip-flop (PTFF) has been successfully used on many high performance and/or low power processors. For instance, on Intel's Pentium processor chips more than 90% of the flip-flop adopts PTFF architecture. Besides improving system performance, it also reduces power consumption and can resolve incurred cooling and chip packaging issues.
In the conventional design of PTFF the generated pulse is maintained at the same width and intensity. However, the flip-flop used on high order system circuits do not maintain a constant triggered operation, but always in a standby state. Since the pulse clock of PTFF is maintained at the same width and intensity, extra power loss incurs. While PTFF can improve some drawbacks of the conventional flip-flop as previously discussed, at present there are no design and research reports that have announced regard changing circuit pulse width and intensity according to input data of flip-flop.